Part Number

IPC-IP-TCP10G

Description

Modern embedded systems are requiring more and more IO bandwidth. High-speed data transport might be an issue if a sufficiently powerful CPU is not available in a system. Hopefully, this is not a problem anymore if the high-speed data transport task is fully offloaded in a dedicated hardware. And the Ipctek's ten-gigabit processor-less Internet TCP/UDP/IP protocol stack can be a good answer for the problem. The whole ten-gigabit TCP/UDP/IP protocols are implemented within a tiny footprint on the FPGA, which makes the IP core perfectly suitable for either prototyping applications or industrial products.

The UDP/IP stack is designed to achieve a near-line-rate throughput performance. An innovative architecture using a two-level cache for the MAC-IP address routing table allows one UDP transmitter instance to support up to 8 different destinations without having to consult the main RT each time the destination changes. As for the TCP/IP stack, slow start, congestion avoidance, duplicate ACK detection, fast retransmission and out-of-order packets reassembling techniques are implemented. This offers both the reliability and an outstanding throughput performance to a connection. As long as the TCP Tx buffer covers the segment's round trip time, a near-line-rate throughput is achieved.

Key Features

  • Compliant to IEEE 802.3 Ethernet packet encapsulation. IP version 4 is supported
  • Echo Reply, ARP, UDP transmitter, UDP receiver and TCP server/client are supported
  • One instance of the UDP transmitter supports up to 8 different destinations without reducing global throughput thanks to a two-level ARP cache implementation
  • UDP TX latency         : 22 clock periods (140.8 ns)
  • UDP TX throughput : 9.88 Gbps with 8950-byte packets
  • UDP RX latency         : 18 clock periods (115.2 ns)
  • TCP TX latency          : 12 clock periods (76.8 ns)
  • TCP TX throughput  : 9.85 gbps with 8936-byte segments. This throughput is sustained as long as the TX buffer size is larger than the segment's round trip time
  • TCP RX latency          : 26 clock periods (166.4 ns)
  • A TCP server can be switched to a TCP client and vice versa in real time
  • TCP Slow Start, Duplicate ACK Detection, Fast Retransmission and Out-of-order packets reassembling techniques are implemented for an optimum TCP transmission
  • Jumbo frame is supported
  • Designed to directly interface with the Xilinx 10G/25G Ethernet Subsystem. The AXI4 Stream interface is used for seamless integration

Example Designs and IP Evaluation

We give several example designs so that users can evaluate the IP core and at the same time practical use cases can be demonstrated. All the design source code and an evaluation netlist can be requested by sending an e-mail to contact@ipctek.net. Upon requesting example designs and/or an evaluation IP netlist, the user MUST accept the IPCTEK's end-user software license terms given in the following documents: French version, English version

  • RTL example design: we show how to interface with the IP core in a pure RTL design. A 10G Traffic Generator is implemeted in order to generate UDP and TCP data. This example design is a good starting point for applications where an extremely high throughput is required.
    • Near-line-rate throughput performance
    • AXI4-Lite wrapper
    • C API for IP core configuration
    • Perfect for high-speed data transfer
  • Microblaze example design: we show how to send/receive UDP and TCP data directly from the Microblaze. We implement an Ethernet Buffer which manages the Tx/Rx data directly in the FPGA programmable logic. On the Microblaze side, we give the user a socket-like C API in order to send/receive UDP and TCP data. Within several simple function calls just like with a native Windows or Linux socket, the user can send/receive data to/from the FPGA TCP/UDP/IP stack. With this design, the users' effort to integrate the TCP/UDP/IP FPGA IP core into their system is reduced to the minimum. For remote control embedded applications, this example design is a plug-and-play solution. The API can be easily ported to other platforms such as Zynq or PCIe Endpoint (smart NIC applications).
    • Socket-like C API. All hardware-related jobs are abstracted
    • Very simple utilization
    • AXI4-Lite wrapper
    • Perfect for remote-control applications

Documentations

Deliverables

  • VHDL source code and/or netlist
  • AXI4-Lite wrapper
  • Bare-metal Board Support Package
  • Socket-like C API
  • Example designs and scripts

Pricing

  • Contact us for details

License

  • Upon purchase, the client MUST accept the IPCTEK's end-user software license terms given in the following documents: French version, English version