Part Number

IPC-IP-TCP1G

Description

The TCP-UDP-IP Stack 1G core implements a high-performance processor-less Internet TCP-UDP-IP protocol stack. The whole Gigabit TCP/IP and/or UDP/IP protocols are implemented within a tiny footprint on the FPGA, which makes the IP core perfectly suitable for either prototyping applications or industrial products.

The UDP/IP stack is designed to achieve near-line-rate throughput performance. As for the TCP/IP stack, as long as the TCP transmitter buffer covers the packet round trip time, a near-line-rate throughput can be achieved.

Key Features

  • Compliant to IEEE 802.3 Ethernet packet encapsulation, IP version 4
  • Echo Reply, ARP, UDP transmitter, UDP receiver, TCP server/client are supported
  • One instance of UDP transmitter supports up to 8 different destinations without reducing the global throughput thanks to a two-level ARP cache implementation
  • UDP TX latency         : 21 clock periods (168 ns)
  • UDP TX throughput : 968 Mbps with 1450-byte frames
  • UDP RX latency         : 54 clock periods (432 ns)
  • TCP TX latency          : 13 clock periods (104 ns)
  • TCP TX throughput  : 958 Mbps with 1450-byte segments. This throughput is sustained as long as the TX buffer size is larger than the segment's round trip time
  • TCP RX latency          : 42 clock periods (336 ns)
  • A TCP server can be switched to a TCP client and vice versa in real time
  • TCP Slow Start, Duplicate ACK Detection, Fast Retransmission and Out-of-order packets reassembling techniques are implemented for an optimum TCP transmission
  • Jumbo frame is supported
  • Designed to directly interface with the Xilinx Trimode Ethernet MAC. The IP core uses the AXI4 Stream interface for seamless integration

Example Designs and IP Evaluation

We give several example designs so that users can evaluate the IP core and at the same time practical use cases can be demonstrated. All the design source code and an evaluation netlist can be requested by sending an e-mail to contact@ipctek.net. Upon requesting example designs and/or an evaluation IP netlist, the user MUST accept the IPCTEK's end-user software license terms given in the following documents: French version, English version

  • RTL example design: we show how to interface with the IP core in a pure RTL design. A traffic generator is implemeted in order to generate UDP and TCP data. This example design is a good stating point for applications where a very high throughput is required.
    • Near-line-rate throughput performance
    • AXI4-Lite wrapper
    • C API for IP core configuration
    • Perfect for high-speed data transfer
  • Microblaze example design: we show how to send/receive UDP and TCP data directly from the Microblaze. We implement an Ethernet Buffer which manages the Tx/Rx data directly in the FPGA programmable logic. On the Microblaze side, we give the user a socket-like C API in order to send/receive UDP and TCP data. Within several simple function calls just like with a native Windows or Linux socket, the user can send/receive data to/from the FPGA TCP/UDP/IP stack. With this design, the users' effort to integrate the TCP/UDP/IP FPGA IP core into their system is reduced to the minimum. For remote control embedded applications, this example design is a plug-and-play solution. The API can be easily ported to other platforms such as Zynq or PCIe Endpoint (smart NIC applications).
    • Socket-like C API. All hardware-related jobs are abstracted
    • Very simple utilization
    • AXI4-Lite wrapper
    • Perfect for remote-control applications

Documentations

Deliverables

  • VHDL source code and/or netlist
  • AXI4-Lite wrapper
  • Bare-metal Board Support Package
  • Socket-like C API
  • Example designs and scripts

Pricing

  • Contact us for details

License

  • Upon purchase, the client MUST accept the IPCTEK's end-user software license terms given in the following documents: French version, English version