Part Number

IPC-IP-5G-NR-LDPC

Description

The IPCTEK’s 5G-NR High Rate LDPC FPGA IP cores implement the LDPC encoder and decoder of the 5G-NR code as described in the 3GPP TS 38.212, section 5.3.2. The IP cores support the base graph 1, lift size 384 and high-rate matrix part, code rate 22/24.

With IPCTEK's universal LDPC frame work, the cores are easily adapted to support any base graph, any code rate and lift size value.

The LDPC encoder achieves an encoding speed of 15.0 Gbps (at clock frequency 280 MHz) while minimizing the utilization of LUTs and registers resource.

At 280 MHz clock, 6 iterations, a decoding speed of 2.69 Gbps (information bits) is achieved. In Ultrascale/Ultrascale+ devices, the decoder can work at more than 280 MHz.

Key Features

  • Compliant to the 5G-NR LDPC of 3GPP TS 38.212 standard. Support the shortened (8448, 9216) code, base graph 1 (high-rate part), lift size 384
  • Universal LDPC frame work. The code is easily adapted to support any base graph, any code rate and any lift size value
  • Highly portable VHDL code, no Xilinx primitive is used
  • Delivered along with a bit-accurate graphical C++ simulation software. Decoding ROM can be generated to support both base graphs 1&2 and any lift size values
  • At 280 MHz clock, an encoding speed of 15.0 Gbps (information bits) is achieved. The encoder is highly optimized, which consumes less than 3k LUTs and 3k registers
  • State-of-the-art layered decoding method was implemented. The decoder has a very fast convergence speed. Almost all the code words are found after 6 iterations at the waterfall region
  • Normalized (scaled) Min-Sum (NMS) decoding algorithm, which is a good performance-complexity compromise, is used. Another advantage is that the NMS algorithm is not sensible to the channel’s LLR scaling
  • At 280 MHz clock, 6 iterations, a decoding speed of 2.69 Gbps (information bits) is achieved. In Ultrascale/Ultrascale+ devices, the decoder can work at more than 280 MHz
  • Optional on-the-fly early stopping technique, increasing the average decoding speed
  • Statistic interface for useful decoding information
  • AXI4 Stream in/out data interfaces for seamless integration

Example Designs and IP Evaluation

We give an example design where we simulate an Addictive White Gaussian Noise so that users can evaluate the IP core and discover how to interface with it. All the design source code can be requested by sending an e-mail to contact@ipctek.net. Upon requesting example designs and/or an evaluation IP netlist, the user MUST accept the IPCTEK's end-user software license terms given in the following documents: French version, English version

Documentation

Deliverables

  • VHDL source code and/or netlist
  • Bit-accurate C++ simulation model
  • AXI4-Lite wrapper
  • Bare-metal Board Support Package
  • Example designs and scripts

Pricing

  • Contact us for details

License

  • Upon purchase, the client MUST accept the IPCTEK's end-user software license terms given in the following documents: French version, English version